Conventional I/O buffers can include circuitry (typically in the I/O portion of an integrated circuit) to provide fast translation between core and external signals. Core signals may have lower voltage differential signaling levels, for example between 0 and 1 V, whereas external output signals may have higher voltage signaling, for example ranging between 0 and 3.3 V.
FIG. 1 illustrates a conventional translation scheme in conventional I/O buffer 10. Core differential signals X/XB are provided to gates of transistors N1/N2, respectively. The drains of N1 and N2 are coupled to nodes D and B, respectively. The external signal output OUT is provided from node B in this example. In accordance with the state of the input differential signals X/XB, therefore, either N1 or N2 will turn on, pulling either node D or B toward Vss, respectively. Nodes D and B are further respectively coupled to the gates of P2 and P1. Accordingly, if D is pulled toward Vss (having a value of about 0 V, for example) by action of N1 and signals X/XB, P2 will turn on, pulling node B (and thus external signal OUT) toward Vdd (having a value of about 3.3 V, for example). Conversely, if node B is pulled toward Vss (and thus external signal OUT) by action of N2 and signals X/XB, P1 will turn on, pulling D toward Vdd, and further turning off P2.
One problem with the conventional approach is that transistors with sufficient voltage ratings to tolerate the higher voltage output usually have high threshold voltages. Transistors with low threshold voltage and high breakdown voltage are either not available or are a costly process option. When X/XB are core differential signals having a maximum signaling value of about 1V, N1 and N2 are only driven weakly by signals X/XB because of the threshold voltage being so high. The result is slow responsiveness, which is a problem in, for example, applications where fast translation is desired.